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MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65667SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION
The M65667SP is a NTSC PIP (Picture in Picture) signal processing LSI, whose sub and main-picture inputs are composite and Y/C separated signals, respectively. The built-in field memory (96k-bit RAM) ,V-chip data slicer and analog circuitries lead the PIP system low cost and small size.
PIN CONFIGURATION (TOP VIEW)
AVss3 (vcxo) VCXO out VCXO in FILTER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 AVssf (ana)
51 Cin 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 TESTEN Yin TEST9 Y-PIP TEST8 C-PIP AVdd4 (da) C-PIPin AVss4 (da) Y-PIPin ADJ-Ysub Yout-sub ADJ-Csub Cout-sub DVss3 DVdd3 LOCK/TEST7 VD/CSYNC/TEST6 HD/TEST5 SWM/TEST4 MCK fsc/TEST3 BGP(m)/TEST2 DVdd2 (ram)
FEATURES
BIAS AVdd3 (vcxo) AVdd2 (m) Vin (m) Vrt (m) Vrb (m) AVss2 (m) AVdd1 (s) Vin (s) Vrt (s) Vrb (s) AVss1 (s) RESET DVss1 DVdd1 BGP(s)/TEST0
* * * * * *
Built-in 96k-bit field memory (sub-picture data storage) Internal V-chip data slicer (for sub-picture) Pin compatible with M65617SP Vertical filter for sub-picture (Y signal ) Single sub-picture (selectable picture size : 1/9 , 1/16) Sub-picture processing sepecification (1/9 size / 1/16 size) : Quantization bits Y, B-Y, R-Y : 6bits Horizontal sampling 171 pixels (Y) , 28.5 pixels (B-Y, R-Y) Vertical lines 69/ 52 lines Frame (sub-picture) on/off Built-in analog circuits : Two 8-bit A/D converters (main and sub-picture signals) Two 8-bit D/A converters (Y and C sub-picture signals) Sync-tip-clump, VCXO, Analog switch ... etc. I2C BUS control (parallel/serial control) : PIP on/off , Sub-picture size(1/9 or 1/16), Frame on/off (programmable luma level), PIP position (4 corners fixed position), Picture freeze , Y delay adjustment, Chroma level, Tint, Black level, Contrast ... etc.
M65667SP
* *
*
APPLICATION
NTSC color TV
SCK CSYNC(s)/TEST1
RECOMMENDED OPERATING CONDITION
Supply voltage range........................................................3.1 to 3.5V Operating frequency.........................................................14.32 MHz Operating temperature....................................................-20 to 75C Input voltage (CMOS interface) "H"........................V DDx0.7 to VDD V "L".............................0 to VDDx0.3V Output current (output buffer)........................................ 4mA (MAX) Output load capacitance............................................20pF (MAX)
1
ACK DATA CLK DVss2 (ram)
Outline 52P4B
Circuit current.........................................................................160mA NOTICE: Connect a 0.1F or larger capacitor between VDD and VSS pins. 1 : Include pin capacitance (7pF)
1
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65667SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
BLOCK DIAGRAM
SCK CSYNC(s) /TEST1 BGP(s) /TEST0
Yin Sync tip Clamp Cin Vdd / Vss for test DATA CLK ACK Vin(s) Sync tip Clamp Vrt(m) Vrb(m) 2 HD (I C) ADJ-Ysub Yout-sub D/A 8bit D/A 8bit HPLL 4fsc Delay Encode 6 Y Demux RAM 96Kbits
2
Y- PIP Bias RAM(1H) C- PIP
15 3 3 I2C I/F A/D 8bit V-chip data slicer Luma Clamp Delay Y 6 Back Porch Clamp
Bias
C- PIPin
Y Y/C SEP (LPF,BPF)
Y- PIPin
Vert-filter Sync Sep AFC Timing Gen (Decode) B-Y Demod Tint R-Y 6 6 Y B-Y R-Y Delay MIX Delay LPF &MPY Level Detect & MUX
Phase Select
C
SWMG /TEST7 Timing Gen (Memory Cont) VD /CSYNC /TEST6 HD /TEST5 FILTER
6 B-Y 6 R-Y
Cout-sub
fsc
ADJ-Csub Vin(m) Bias A/D 8bit
Burst Data Sampling
Phase Detect Lock/Free-run via I2C VCXO Driver
4fsc VCXO
BIAS VCXO in VCXO out
Vrt(m) Vrb(m)
2
RESET
MCK
BGP(m) /TEST2
fsc /TEST3
SWM /TEST4
2
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65667SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION OF PIN
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Name AVss3 (VCXO) VCXO out VCXO in FILTER BIAS AVdd3 (VCXO) AVdd2 (m) Vin (m) Vrt (m) Vrb (m) AVss2 (m) AVdd1 (s) Vin (s) Vrt (s) Vrb (s) AVss1 (s) RESET DVss1 DVdd1
BGP(s)/TEST0
SCK
CSYNC(s)/TEST1
ACK DATA CLK DVss2(ram) DVdd2(ram)
BGP(m)/TEST2
I/O GND O I I O Vdd Vdd I O O GND Vdd I O O GND I GND Vdd (I/)O I I(/O) O I I GND Vdd (I/)O I(/O) I (I/)O I(/O) I(/O) I(/O) Vdd GND O I O I I GND I Vdd O I O I I I I Vss
Function Connects to analog GND VCXO output signal VCXO input signal Filter Bias Connect to analog power supply Connect to analog power supply Chroma signal input (main-picture) A/D Vref+ (main-picture) A/D Vref- (main-picture) Connect to analog GND Connect to analog power supply Composite video signal input (sub-picture) A/D Vref+ (sub-picture) A/D Vref- (sub-picture) Connect to analog GND Power on reset input signal ("L" reset) Connect to digital GND Connect to digital power supply For test For test (connect to digital GND) For test (connect to digital GND) I2C bus-data/Acknowledge output signal I2C bus-data input signal I2C bus-clock input signal Connect to digital GND Connect to digital power supply For test For test (pull down to digital GND by resistor 15k ) For test (connect to digital GND) For test Horizontal sync input signal (Positive going edge is used) Vertical sync input signal (active "H") Enable input signal to display sub picture ("H" enable) Connect to digital power supply Connect to digital GND D/A output signal (Chroma signal of sub-picture) D/A adjust for chroma signal (sub-picture) D/A output signal (Luma signal of sub-picture) D/A adjust for luma signal (sub-picture) PIP luma signal re-input Connects to analog GND PIP chroma signal re-input Connect to analog power supply PIP chroma signal output For test (connect to analog GND) PIP luma signal output For test (connect to analog GND) Luma input signal (main-picture) For test (connect to analog GND) Chroma input signal (main-picture) Connect to analog GND
Remarks
100k to VDD,10F to GND
non connect connect to GND pull down 15k
fsc/TEST3 MCK SWM/TEST4 HD/TEST5 VD/CSYNC /TEST6
SWMG/TEST7
non connect pull down 15k connect to GND non connect
pull up 15k
DVdd3 DVss3 Cout-sub ADJ-Csub Yout-sub ADJ-Ysub Y-PIPin AVss4 (da) C-PIPin AVdd4 (da) C-PIP TEST8 Y-PIP TEST9 Yin TESTEN Cin AVssf (ana)
pull up 15k connect to GND connect to GND
3
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65667SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
ABSOLUTE MAXIMUM RATINGS (VSS=0V)
Symbol VDD3 VI VO IO Pd Topr Tstg Parameter Supply voltage (3.3V) Input voltage Output voltage Output current (1) Power dissipation Operating temperature Storage temperature Limits Min. Max. -0.3 -0.3 -0.3 - - - -20 -50 4.6
VDD3+0.3 VDD3+0.3
Unit V V V mA mW C C
IOL=20 IOH=-26 1400 75 125
1: Output current per output terminal. But Pd limits all current.
DC CHARACTERISTICS (Ta=25C, unless otherwise noted, VSS=0V)
Symbol VIL VIH VTV T+ VH VOL VOH IOL IOH IIH IIL IOZL IOZH CI CO CIO IDD Parameter Input voltage (CMOS interface) Input voltage schmitt trigger (CMOS interface) Output voltage Output current Input current Output leakage current Input pin capacitance Output pin capacitance Bidirectional pin capacitance Operating current L H - +
Hysteresis
Test conditions VDD=2.7V VDD=3.6V VDD=3.3V
L H L H L H L H
VDD=3.3V, | IO | <1A VDD=3.0V, VOL=0.4V VDD=3.0V, VOH=2.6V VDD=3.6V, VI=0V VDD=3.6V, VI=3.6V VDD=3.6V, VO=0V VDD=3.6V, VO=3.6V f=1MHz, VDD=0V
Min. 0 2.52 0.5 1.4 0.3 - 3.25 4 - -1 -1 -1 -1 - - - -
Limits Typ. - - - - - - - - - - - - - 7 7 7 -
Max. 0.81 3.6 1.65 2.4 1.2 0.05 - - -4 1 1 1 1 15 15 15 140
Unit V V V V V V V mA mA A A A A pF pF pF mA
3.3V supply
TYPICAL CHARACTERISTICS
THERMAL DERATING (MAXIMUM RATING)
2000
POWER DISSIPATION Pd (mW)
1600 1490 1200
800
400
0 0 25 50 75 100 125
AMBIENT TEMPERATURE Ta (C)
4
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65667SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
APPLICATION EXAMPLE
Horizontal sync input signal (main-picture) Vertical sync input signal (main-picture)
Chroma input signal (main-picture)
Luma signal input (main-picture)
Ana. 68p Ana. Ana. 150p 360 Dig 470
104
104
10
Ana. 103 15k
104 104 103 103
Sub-picture displaying on/off
PIP Chroma signal output
PIP Luma signal output
Dig 15k 103 10
10 103
52
50
45
40
35
30
27
M65667SP
1
5
470k
10
15
20
26
14p 51 Digital +3.3V power supply Digital GND Ana. Analog +3.3V power supply Analog GND 330 104
100k
2k 103 3.3
104 103 103
103 103
10 103 Ana. Ana.
10 103 104
100k Dig5V Dig5V
10 103
47k
12k
47k
Ana. 10 Dig SYNC SEP CIRCUIT (OPTIONAL)
330 560 100
100
10k 100 SDA SCL
12k
10k
Composite video input signal (sub-picture)
I2C BUS Clock input signal I2C BUS DATA input /output signal
Separate Y/C signals by using LC-tank circuit or LPF,BPF for Y/C signals level adjust. And then mix both signals for sub-picture input video signal. Units Resistance : Capacitance : F
5
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65667SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
PIP TV SYSTEM BLOCK DIAGRAM
(BASIC) Composite Video Signal Y C C C BLPLL B-LD Y C CV Y PIP Signal Processing C
Y/C Separation
Y
M65667SP
Y
Video Signal Processing
Deflection Unit Yoke
Y/C Separated Video Signal
HD
VD
(Driving Method and Operating Specification for Serial Interface Data)
(1) Serial data transmission completion and start A low-to-high transition of the DATA (serial data) line while the CLK (serial clock) is high, that completes the serial transmission and makes the bus free. A high-to-low transition of the DATA line while the CLK is high, that starts the serial transmission and waits for the following CLK and DATA inputs. (2) Serial data transmission The data are transmitted in the most significant bit (MSB) first by one-byte unit on the DATA line successively. One-byte data transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter one is for acknowledge detection. (In reading state, ACK is 'H' under these two conditions ; 1) the coincidence of two address data for the address data transmission, 2) the completion of 8-bit setting data transfer. In writing state, ACK is 'H' with the address coincidence and ACK is 'L' for detecting acknowledge input from the master (micro processor) after sending 8-bit setting data.) For address/data transmission, DATA must change while CLK is 'L'. (The data change while CLK is 'H' or the simultaneous change of CLK and DATA, that will be a false operation because of undistinguished condition from the completion/start of serial data transfer). After the beginning of serial data transmission, the total number of data bytes that can be transferred are not limited. (3) The byte format of data transmission (The sequence of data transmission) 1. The byte format during data setting to M65667SP are shown as follows.
In right after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred. Afterwards, the internal register address (1 byte) and setting data (by 1 byte unit) are transferred successively. Several bytes of setting data can be handled in the one transmission. In this operation, the setting data are written into the address register whose address is increased one in initially transferred internal register address. (The next address of 7Fh, it returns to 00h). 2. The byte format during data reading from M65667SP are shown as follows. Before data reading from M65667SP, whose internal address need to be set by the data reading/transmitting. After the data reading/ transmitting, the operation of "serial data transmission completion and start" (described in (1)) is necessary. Continuously, the slave address 25h (00100101b) is sent, and then the inverted read out data are available on ACK. Several bytes of writing data can be handled in the one transmission, too. In this operation, the setting data also are written into the address register whose address is increased one in initially transferred internal register address. (The next address of 7Fh, it returns to 00h).
6
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65667SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
(The examples of serial byte transmission format)
(1) The writing operation of the setting data (AAh) into M65667SP internal address of 00h
Transmission Activation
Confirmation of bus free (DATA='H')
yes S 24h A 00h A AAh ADE
no S : Operation of serial transmission start is applied on CLk for the release of output state A : Acknowledge detection D : Dummy clock feed for the release of acknowledge output state E : Operation of serial transmission completion
(2) The writing operation of the setting data (FFh, 80h, EEh) into M65667SP internal address of 04h to 06h
Transmission Activation
Confirmation of bus free (DATA='H')
yes S 24h A 04h A FFh A 80h A EEh ADE
no is applied on CLk for the release of output state
(3) The reading operation of the setting data from M65667SP internal address of 00h
Transmission Activation
Confirmation of bus free (DATA='H')
yes S 24h A 00h ADE S 25h A $$h A'
no A' : Bus free operation by the is applied on CLk for the release of output state master (micro processor)
7
MITSUBISHI ICs (TV)
PRELIMINARY
Notice:This is not a final specification. Some parametric limits are subject to change.
M65667SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
(4) The reading operation of the setting data from M65667SP internal address of 04h to 06h
Transmission Activation
Confirmation of bus free (DATA='H')
yes S 24h A 04h ADE S 25h A SSh A'' SSh A'' SSh A'
no A'' : Output `L' operation by the is applied on CLk for the release of output state master (micro processor)
TIMING DIAGRAM
1 2 3 4 5 6 7 8 9 1
CLK
DATA
Bit7 (MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 (LSB)
ACK Detec.
Bit7 (MSB)
ACK _ Acknowledge
ACK _ Readout data
Bit7 (MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 (LSB)
Bit7 (MSB)
8

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